June 12-13, 2016
Honolulu, USA

General Information

The 2016 Silicon Nanoelectronics Workshop is a satellite workshop of the 2016 VLSI Symposium sponsored by the IEEE Electron Device Society. It will be held on June 12-13, 2016 at the Hilton Hawaiian Village in Honolulu, Hawaii USA. This will be the 22nd workshop in the annual series. Original papers on nanometer-scale devices and technologies that utilize silicon or which are based on novel materials on silicon substrates are welcome.


  • Nanometer-scale transistors, including those employing non-classical structures, novel channel and source/drain materials, or non-thermal injection mechanism.
  • Junction and insulator materials and process technology for nanoelectronic devices.
  • Techniques for fabrication of nanostructures, including nanometer scale patterning.
  • Physics of nanoelectronic devices, e.g. quantum effects, non-equilibrium transport.
  • Modeling and simulation of nanoelectronic devices, e.g. including atomistic effects.
  • Nanoscale surface, interface, and heterojunction effects in devices.
  • Device scaling issues including doping fluctuations and atomic granularity.
  • Circuit design issues and novel circuit architectures, including quantum computing, for nanoelectronic devices.
  • Optoelectronics using silicon nanostructures.
  • Techniques targeting zero power electronics (self-supplying), including wireless sensors, energy harvesting, steep slope devices, ultra-low power design and devices.
  • Devices for 3D and heterogeneous integration on Silicon, including Graphene, III-V devices, CNT, spin-based devices, MEMS and NEMS, etc.
  • Novel transistors based on two dimensional materials, e.g. MoS2, WS2, etc.
  • Integrated energy harvesting and energy storage based on new material and structures.
  • Low power integrated sensors for Internet-of-Things.

Final call for papers

Click here to download.

Keynote Speakers

Transport in non-conventional FETs

Joerg Appenzeller
Purdue University,
West Lafayette,
Indiana, 47907

Devices and Circuits at the End of Scaling

David J. Frank
IBM Research Division, Yorktown Heights,
New York, 10598